Talk:Transition-minimized differential signaling

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Clarification request

I wonder about the sentence "The physical layer for TMDS is current mode logic (CML), DC coupled and terminated to 3.3 Volts.", could the second part be clarified? CML has a link with further information, but though I am interested in electronics and (almost) obsessed with computers I am not sure how to interpret DC coupled or terminated to 3.3 Volts.
(So far I imagine that it could mean that there are no decoupling capacitors, meaning that the actual DC level will be shared/transferred over the physical medium, and maybe that both sides are supposed to attempt to keep each line at a 3.3V DC bias/offset.)
I find no useful or unambiguous reference for DC coupled on Wikipedia, and a clarification in this context would at least be helpful for me. --Johan Adler (talk) 09:11, 14 August 2012 (UTC)[reply]

This article is not in great shape and makes you work. I don't have time to make necessary improvements now but I have added a couple links to the sentence that I hope will send you in the right directions for answers. --Kvng (talk) 15:37, 16 August 2012 (UTC)[reply]

Please see this article on Capacitive Coupling: http://en.wiki.x.io/wiki/Capacitive_coupling. Capacitive coupling is also referred to as AC coupling, as only a time-varying signal can pass through the coupling capacitor. Capacitive coupling will not pass the DC level of a signal, but will pass the AC component. DC coupling does not use a capacitor, but a direct or conductive or resistive coupling so that both the AC and DC components of a signal are passed. These terms are very commonly used in both analog and digital electronics, so by performing searches on Capacitive Coupling, AC Coupling, and DC Coupling elsewhere on the Internet and in other reference material, you should be able to learn about this subject. Agrjlc (talk) 20:55, 27 June 2013 (UTC)[reply]

Current Mode Logic

The article states "The physical layer for TMDS is current mode logic (CML)..." I would like to see citation to support and provide understanding for this assertion. The referenced Digital Visual Interface specification document states in section 4.1, page 33, "T.M.D.S. technology uses current drive to develop the low voltage differential signal at the receiver side of the DC-coupled transmission line." It does not use the term "Current Mode Logic." Furthermore, the diagram in Figure 4-1 shows the link with pull-ups only at the Receiver side; the transmitter can pull down each conductor through a current sink to ground. This diagram does not show pull-ups on the transmitter side.

Maxim AN291, (http://pdfserv.maxim-ic.com/en/an/AN291.pdf) referenced in the Current Mode Logic article, shows in Figure 3 on page 3, a CML output structure that includes 50 ohm pull-ups on both the output (transmitter) and input (receiver.) So are there different drive types of CML, and can it include the variety shown in the DVI document, with no pull-ups on the transmitter side? If so, I would like to see a supporting citation. Or perhaps it is not correct to say that the TMDS physical layer is CML, and the DVI document is correct in using the term "current drive" to indicate something that may be similar to CML, but not the same.

Also note that the article on Current Mode Logic has the same issue. Agrjlc (talk) 20:55, 27 June 2013 (UTC)[reply]

Here's a TI datasheet for a DVI/HDMI Retimer that shows the three differential pairs are in fact using CML: http://www.ti.com/lit/ds/symlink/ds34rt5110.pdf There are similar results from Maxim and others. I think it's clear enough that CML is the transport layer, so I'm going to remove the dubious tag and use the datasheet as a citation. Timbdotus (talk) 06:56, 16 September 2013 (UTC)[reply]

Thank you Timbdotus, your citation strengthens the article.Agrjlc (talk) 18:41, 1 November 2013 (UTC)[reply]

Voltage Swing?

Which is the voltage swing of the signals? Is this variant oder constant / well defined for HDMI? The LVDS specification ist not clear. 213.61.254.68 (talk) 14:12, 26 September 2019 (UTC)[reply]