James Hoe

James C. Hoe
Born	April 1970 (age 54) Taiwan
Alma mater	University of California, Berkeley (undergrad), Massachusetts Institute of Technology (graduate)
Awards	Fellow of the IEEE
Scientific career
Fields	Computer architecture, reconfigurable computing, high-level synthesis
Institutions	Carnegie Mellon University
Doctoral advisor	Arvind
Website	users.ece.cmu.edu/~jhoe

James Hoe is a Taiwanese-American professor of Electrical and Computer Engineering at Carnegie Mellon University (CMU). He is interested in many aspects of computer architecture and digital hardware design, including the specific areas of field-programmable gate array (FPGA) architecture for computing; digital signal processor (DSP) hardware; and high-level hardware design and synthesis. Professor Hoe’s current research focus is on devising a new FPGA architecture for power efficient, high-performance computing. His research group is working on developing an FPGA runtime environment that incorporates partial reconfiguration, virtualization, and protection features to manage an FPGA as a dynamically sharable multitasking compute resource.

Academic biography

He received his B.S. in EECS from the University of California, Berkeley in 1992 and Ph.D. in EECS from Massachusetts Institute of Technology (MIT) in 2000. Since 2000, he has been with the Electrical and Computer Engineering Department of Carnegie Mellon University. He became a full professor in 2009 and an IEEE Fellow in 2013. He was the Associate Head of the Electrical and Computer Engineering Department at Carnegie Mellon University from 2009 to 2014.

Resesarch

He has worked on a wide range of research projects at Carnegie Mellon University. He currently leads the Crossroads 3D-FPGA Academic Research Center to investigate a new programmable hardware data-nexus lying at the heart of the server and operating over data ‘on the move’ between network, traditional compute, and storage elements. His efforts towards researching FPGA Architecture for Computing include the CoRAM FPGA computing abstraction, the Pigasus Network function acceleration, Service-Oriented Memory Architecture and Programmable and Dynamic Computing Deployment projects. Since 2003, he has been a faculty member in the SPIRAL project researching domain-specific hardware synthesis for digital signal processing. Between 2005 and 2011, his group worked on the Protoflex technology to accelerate the functional-only simulation using a multithreaded implementation of the SPARC V9 ISA in field-programmable gate arrays (FPGAs). Between 2002 and 2006, he worked on sampling-based performance simulation of computer systems (SMARTS) that uses functional-only simulation to keep caches warmed up between detailed simulation phases.

While a graduate student at MIT, he initially worked on high-performance system area network for computer clusters (StarT-Jr and Start-X). For his Ph.D. thesis, he worked on high-level synthesis from hardware descriptions based on term rewriting systems (TRS). This synthesis system is the basis of the Bluespec SystemVerilog programming language and compiler, a Haskell extended to for chip design and electronic design automation, by Bluespec, Inc.