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Stories about the phase shift between the current and voltage

Why there is a phase shift between the current and voltage in a capacitor

(an intuitive explanation by using hydraulic analogy)

IMO it would be interesting to see the correspondence below between me and a curious web reader about the phase shift phenomenon in capacitors driven by AC. Circuit dreamer (talk, contribs, email) 09:38, 26 June 2011 (UTC)[reply]

QUESTION: Im having a really hard time trying to understand what the phase shifts mean in real life in a circuit (I know it means current lags source voltage by X amount..but how). I understand them mathematically but not in physicality, mainly because I cant find any explanation.

ANSWER: Let's explain for now the 90 deg phase shift between current and voltage in a capacitor. I recommend to you to think "hydraulically" ("electrical current - water flow" and "voltage - water level") to understand intuitively the phase shift idea.

Well, imagine you fill (sinusoidally) a vessel with water and you picture graphically this process. Choose the half of the maximum water height as a zero level (ground). So, you first open and then close (sinusoidally) the supply faucet. But note no matter you close the faucet (in the second part of the process) the level of the water will continue rising; it is strange that you close the faucet but the water continue rising. Finally, you have completely closed the faucet (zero current), but the level of the water will be maximum (maximum voltage).

Now, at this point, you have to change the flow (current) direction to make the water level decrease. For this purpose, you open and then close another faucet at the bottom to draw the water (now you draw current from the capacitor). But again, no matter you close the faucet the level of water will continue falling; it is strange again that you close the faucet but the water continue falling. Finally, you have completely closed the faucet (zero current), but the level of the water will be maximum negative (maximum negative voltage).

So, the basic idea behind all kind of such storing elements (named integrators) is:

The sign of the output pressure-like quantity (voltage, water level, air pressure, etc.) can be changed only by changing the direction of the input flow-like quantity (current, water flow, air flow, etc.); it cannot be changed by changing the magnitude of the flow-like quantity. At this point, the current is zero but the voltage is maximum; this gives the 90 phase shift on the graph.

Circuit dreamer (talk, contribs, email) 09:38, 26 June 2011 (UTC)[reply]

QUESTION. ...However, I full understand the phase shift INSIDE the capacitor. That I understand 110%. At the begining there is max current flowing through the capacitor as there is no opposing voltage built up across it. As time goes on the current charges up the capacitor creating a voltage accross it which will then oppose the current. So at max current theres no voltage and at max voltage across it there is no current through it. And thus 90 degree lag....

BUT, what im trying to understand is something slightly different...the bigger picture....total impedance.

So for example, we have a capacitor with reactance of 10 Ohms and a resistor in series of 2 Ohms and an AC source of 10V. The total impedance in the circuit is going to be - Squareroot(10 squared + 2 squared) = 10.198 Ohms at a phase of - inverse tan(-10/2) = -78 degrees. So total impedance = 10.198 Ohms -78 degrees.

So what im trying to work out is WHAT causes this OVERALL lag in the circuit of 78 degrees.

I understand fully the lag inside the capacitor or inductor but when it comes to the overall lag in the circuit, what analogy can be used to discribe THIS lag. What is causing it to be -78 the physical happening of it.

ANSWER. Be patient:)! We will reach the so desired RC phase-shift expalanation (I managed to do this in the early 90's) but let's first explain this phenomenon in the case of the bare capacitor.

As I can see, you have learned very well your lessons about AC supplied capacitors since this is the classic textbook explanation of the phase shift between current and voltage in a "voltage-supplied capacitor". Maybe, it is repeated hundred of thousands or millions times in textbooks through years but it is not the best explanation since this arrangement (AC voltage source driving a capacitor) is just incorrect... You know why - because the current will be unlimited and we have not such huge voltage sources producing current with infinite magnitude. That is why, I have chosen the dual arrangement - a "current-supplied capacitor", to explain why there is an exactlty 90 degree lag. This is the real situation since even real voltage sources have some internal resistance. And what is more important, we will use this arrangement to explain the overall lag (0 - 90 degree) in an RC circuit. So, I suggest to you to repeat my explanations but only in terms of electricity.

Well, imagine we drive the capacitor by a sinusoidal current source. "Current source" means that it produces and passes a sinusoidal current in spite of all. No matter what the voltage (drop) across the capacitor is - zero (empty capacitor), positive (charged capacitor) or even negative (reverse charged capacitor), our current source will pass the desired current with desired direction through the capacitor. This is the difference with your explanation - here the voltage across the capacitor does not impede the current (it impedes but the current source compensates it).

So, until the input current is positive (imagine the positive half-sine wave) it enters the capacitor and its voltage continously increases in spite of the current's magnitude (only the rate of change varies)... Imagine... the current rapidly increases -> slows down -> rapidly decreases... and finally becomes zero. At this moment there is a maximum voltage (drop) across the capacitor.

So, as you have said, "at max voltage across it there is no current through it"...Now the current changes its direction and begins rapidly increasing again -> slows down -> rapidly decreases... and becomes zero again... and again and again and again...

So, in this arrangement, the phase shift is constant and exactly 90 degree because of the ideal input current source that compensates somehow the voltage drop (losses) across the capacitor.

If you have nothing against Wikipedia, I would like to place our conversation there again. My idea is to provoke wikipedians to discuss this so interesting topic and then to add some intuitive explanations in the intro of the article... to make it more human friendly...

Circuit dreamer (talk, contribs, email) 20:30, 26 June 2011 (UTC)[reply]

Wikipedia has an article on the Hydraulic analogy that includes a section about the capacitor. For the example in your question, the reactance of the capacitor depends on ("is a function of") frequency so the RC circuit gives the 78 degree lag only at the particular frequency that you don't mention. This page is about improving the RC circuit article and a conversation about intuitive notions about a capacitor in isolation would not be productive. Cuddlyable3 (talk) 15:56, 28 June 2011 (UTC)[reply]

Thank you for the participation in this so interesting discussion. You are right but my idea is first to consider a bare AC current-supplied capacitor and to explain by intuition why the phase shift is exactly 90 degree and why it does not depend on frequency (the dialog above). Then, in the next dialog, I will consider the simple RC integrating circuit at varying frequency (or different capacitances) and will explain why the phase shift varies as well (depends on frequency). Finally, I will show how to make it not vary again and to stay exactly 90 degree no matter what the frequency is (the basic idea behind the op-amp inverting integrator). It would be great pleasure for me if you and other wikipedians join the discussion. Circuit dreamer (talk, contribs, email) 17:00, 28 June 2011 (UTC)[reply]

But there is no phase shift across a bare capacitor with no resistance in the loop. The current is virtually infinite and therefore voltage in the capacitor follows the supply voltage exactly, with any change in supply met by a change in charge and voltage in the capacitor instantly, due to the infinite current adding charge in infinitesimal time. Now consider adding a reasonable resistance in series with the capacitor. It will take time for charge to build in the capacitor, so its voltage will lag the applied voltage. Now consider a sinusoidally varying source voltage. If it varies very slowly, the capacitor charge has time to almost catch up before the source voltage drops to meet the capacitor voltage and the capacitor charge stalls and then drops. If it varies very quickly, the capacitor charge will not have time to catch up at all and will lag by more relative to the source change. Thus at low frequencies, the voltage lag is relatively small (near 0°) and at high frequencies the lag is relatively large (near 90°). At the limits of 0 frequency and infinite frequency, the voltage phase difference approaches 0° and 90°, respectively. The 'relatively' is important, here, since at high frequencies the time-lag is actually shorter; it's only the phase-lag relative to the source curve that is larger. Also, look at what happens to amplitude. With more time to build, the charge gets larger and the voltage does, too, so the voltage amplitude across the capacitor is larger, and therefore represents more of the total voltage in the circuit. The sum of the capacitor voltage and the resistor voltage is equal to the supply voltage. In terms of a divider circuit when an element holds a larger portion of the total voltage it means that this element has a higher relative impedance. So at low frequencies the impedance of a capacitor is considered to be high. At high frequencies, there is less time for charge to build, so the voltage amplitude across the capacitor is smaller, and thus the capacitor's impedance is considered to be small. 2605:6000:EC07:A400:CD4E:EADE:2B7D:B003 (talk) 20:52, 28 December 2014 (UTC)[reply]

Why there is a variable phase shift of 0 - 90 degree in an RC circuit

Let's now consider the ubiquitous RC circuit. First, let's build it. We have already realized that it is incorrect to drive a capacitor directly by a voltage source; we have to drive it by a current source. For this purpose, let's connect a resistor between the voltage source and the capacitor to convert the input voltage to current; so, the resistor acts as a voltage-to-current converter. From another viewpoint, we have built a current source by the input voltage source and the resistor. Let's now consider the circuit operation (I will do it electrically but the hydraulic analogy of communicating vessels is an impressive way to do it as well).

Imagine how the input voltage V_IN changes in a sinusoidal manner. In the beginning, the voltage rapidly increases and a current I = (V_IN - V_C)/R flows from the input source through the resistor and enters the capacitor; the output voltage begins increasing lazy. After some time, the input voltage approaches the sine peak and then begins decreasing. But until the input voltage is higher than the voltage across the capacitor the current continues flowing in the same direction. As above, it is strange that the input voltage decreases but the capacitor voltage continues increasing. Figuratively speaking, the two voltages move against each other and finally meet. At this instant, the two voltages become equal; the current is zero and the capacitor voltage is maximal. The input voltage continues decreasing and becomes less than the capacitor voltage. The current changes its direction, begins flowing from the capacitor through the resistor and enters the input voltage source. It is very interesting that the capacitor acts as a voltage source that "pushes" a current into the input voltage source acting as a load. Before the source was a source and the capacitor was a load; now, the source is a load and the capacitor is a source...

So, the moment where the two voltages become equal and the current changes its direction is the moment of the maximal output voltage. Note it depends on the rate of changing (the frequency) of the input voltage: as higher the frequency is, as low the maximum voltage across the capacitor is... as later the moment is... as bigger the phase shift between the two voltages is... At the maximal frequency, the voltage across the capacitor cannot move from the ground and the moment of current direction change is when the input voltage crosses the zero (the situation is similar to the arrangement of a current-supplied capacitor).

So, in this arrangement, the phase shift varies from zero to 90 degree when the frequency varies from zero to infinity because of the imperfect input current source that cannot compensate the voltage drop (losses) across the capacitor. Circuit dreamer (talk, contribs, email) 03:29, 5 July 2011 (UTC)[reply]

CD, the point of the response to your dialog above was that this page is for discussing how to improve the article, not for exercises in creative writing. Dicklyon (talk) 05:08, 5 July 2011 (UTC)[reply]

I think I show just how to improve the introductory AC part of the article by extracting some intuitive explanations (of course, in a more concise and appropriate form) from this discussion. This phenomenon (lag) is extremely interesting but unexplained. It would be better if you, relying on your prestige, join the discussion and involve others in it; at least, you may encourage instead to dispirit me to continue. Circuit dreamer (talk, contribs, email) 05:37, 5 July 2011 (UTC)[reply]

Prestige is in no way relevant in WP editing. And there's no discussion here. If you have an idea for something to add to the article, say it, or just add it, and we can discuss when we see it. Dicklyon (talk) 06:16, 5 July 2011 (UTC)[reply]

Theoretically, prestige is (should be) no relevant in WP but practically it is pretty substantial... I have known from my bitter WP experience that the most important things for wikipedians are where you are from, where you graduated from and where you work...

With this exposition I prepare the ground for adding a material. The problem is that the article is so formal, sterile and remote from real life (written only for PhD or EE:) so that it is difficult to make a smooth transition from such intuitive explanations to the next theory. Circuit dreamer (talk, contribs, email) 10:42, 5 July 2011 (UTC)[reply]

We can draw a final conclusion about the AC supplied RC circuit:

Until the input voltage is higher than the voltage across the capacitor the current flows from the input source to the capacitor and the voltage across the capacitor continuosly increases no matter if the input voltage increases or decreases.

Now we can use the acquired here knowledge to explain in such an intuitive way the odd RC "amplifying" circuit above. Circuit dreamer (talk, contribs, email) 10:55, 5 July 2011 (UTC)[reply]

How to make the phase shift in an RC circuit exactly 90 degree

Circuit dreamer (talk, contribs, email) 15:00, 5 July 2011 (UTC)[reply]

I assume you mean the phast shift from input to output in a series RC circuit with the output taken from across the capacitor. You can have a phase shift of exactly -90 degrees in theory only because it would take one value (w, R, or C) to be infinite. You can get close with a large value for C. For example, with w=1, R=1 and C=1000 the phase shift is -89.94 approximately. In this example the larger the value of C the closer the phase fhit will be to -90 degrees. You can also make either R and/or w large to get the same effect. The problem however is that as C, w, or R gets larger the amplitude gets closer to zero so it may do no good to get close to -90 degrees. Oscillator circuits use RC networks that have phase shifts very different than -90 degrees, for example -45 degees. The phase shift can be calculated from ph=-atan(w*R*C), where w=2*pi*f with f in Hertz, R in Ohms, and C in Farads. MrAL Gx (talk) 17:43, 21 March 2021 (UTC)[reply]

PWM averaging

I've removed the following section from the article. It's inserted without context and has a lot of stylistic and editorializing issues, but more than that, it is only tangentially related to the article topic.

PWM Averaging Responses

We begin with the analysis using the capacitor definition:

i=C*dv/dt

In this circuit, the current i is noted to be (E-v)/R if v is the average capacitor voltage and E is a constant DC voltage.. This gives us:

C*dv/dt=(E-v)/R

Since E takes on two values here, both E (a particular DC voltage) and 0 (zero voltage) we need two equations, one when it is E and one when it is zero. The second equation is the same with E set to zero and the polarity of v made positive since when the cap is discharging v is some positive value. This gives us:

C*dv/dt=v/R

Now simply multiply both sides of this set of equations by C (and RC=R*C) we get:

dv/dt=(E-v)/RC (when the PWM input E is high)

and

dv/dt=v/RC (when the PWM input E is zero)

The time increment dt is only the same for a 50 percent PWM duty cycle, so we need a more general expression. For this we simply set each time increment dt to a unique value:

dv/dt1=(E-v)/RC

dv/dt2=v/RC

Now simply solve for dv in each equation:

dv=dt1*(E-v)/RC

dv=dt2*v/RC

Now applying the theory of Continuity of States, we can say that these two values for dv must be the same when the voltage across the capacitor is at its average value. That is because when the voltage goes up starting at a certain lower value it must later come down to the same lower voltage or else the voltage is not yet at its average value. So noting that, we can equate the two:

dt1*(E-v)/RC=dt2*v/RC

and now solving for the average voltage v we get:

v=(dt1*E)/(dt2+dt1)

Now we could stop here and note that v is the average voltage across the cap and dt1 is the 'on' time and dt2 is the 'off' time, but in most cases we want to relate this to the duty cycle D. It is quite simple to note that if we know the total time period tp we can equate these two:

dt1=D*tp

dt2=(1-D)*tp

where D is the fractional duty cycle (0.30 is 30 percent for example) and so substituting those two into the previous solution for v we end up with:

v=(tp*D*E)/(tp*D+tp*(1-D))

and when we simplify this expression we get:

v=D*E

A very simple result! So the average voltage is D*E and we might immediately note that the actual values of R and C did not matter. That is actually the case for any values as long as the capacitor voltage does not get close to zero or E for either the 'on' or 'off' periods. Later when we calculate the peaks, we will find that the R and C values do not matter if RC>>tp but if the RC time constant is comparable to the total time period tp then we will find a difference in the upper and lower peaks of the time domain calculations and the upper and lower peaks of the averaged calculations, although the differences may be small.

A simple example is when E=10v and D=0.25, the average voltage v is 2.5 volts.

Another simple example is when E=20v and D=0.50, the average voltage is 10 volts.

Next we will calculate the two peak values, the upper peak and the lower peak. There are at least two ways to do this one using an averaging technique and another using a straight up time domain solution. The averaging technique assumes a short total time period tp while the time domain solution assumes nothing except ideal components (as is typical in theoretical solutions).

Using the averaging technique, we note that previously we got the result for the low to high going capacitor voltage deviation as:

dv=dt1*(E-v)/RC

and we substituted dt1=D*tp and got:

dv=D*tp*(E-v)/RC

and we assumed that 'v' was the average voltage. Since 'v' was the average voltage and we later calculated that as:

v(avg)=D*E

we insert that into the above expression and end up with:

dv=D*tp*(E-D*E)/RC

or:

dv=D*tp*E*(1-D)/RC

and that is the entire deviation from lowest point to highest point across the capacitor, often referred to as the voltage peak to peak.

Since that is the entire deviation and in the straight line approximation it is triangular and a triangular wave has average that is 1/2 of its entire amplitude peak to peak, to get the excursion above the average we just divide that in half. For the same reason the amplitude below the average will also be one half of that.

We might note that the RC values do in fact make a difference for this calculation even though the did not matter for the average calculation.

Example: R=1000 Ohms, C=100uf, tp=0.001 seconds, E=10 volts, D=0.50 (50 percent duty cycle)

Result: dv=0.025 volts peak to peak.

Positive excursion: 0.025/2=0.0125 volts peak

Negative excursion: 0.025/2=0.0125 volts peak

Also noteworthy is that if we calculate the maximum of dv with respect to a variation in D the duty cycle, we will find that the value of D that causes the highest voltage peak to peak is D=0.50 which is a 50 percent duty cycle.

SpinningSpark 17:27, 3 August 2021 (UTC)[reply]