Motorola 68060

A Motorola 68EC060 microprocessor

The Motorola 68060 is a 32-bit microprocessor from Motorola released in 1994. It is the successor to the Motorola 68040 and is the highest performing member of the 680x0 family. Two derivatives were produced, the 68LC060 and the 68EC060.

Architecture

For more information on the instruction set and architecture, see Motorola 68000.

There is an LC (Low-Cost) version, without an FPU and EC (Embedded Controller), without MMU and FPU. The 68060 design was led by Joe Circello.

The 68060 shares most architectural features with the P5 Pentium. Both have a very similar superscalar in-order dual instruction pipeline configuration, and an instruction decoder which breaks down complex instructions into simpler ones before execution. However, a significant difference is that the 68060 FPU is not pipelined and is therefore up to three times slower than the Pentium in floating point applications. In contrast to that, integer multiplications and bit shifting instructions are significantly faster on the 68060. An interesting feature of the 68060 is the ability to execute simple instructions in the address generation unit (AGU) and thereby supply the result two cycles before the ALU. Another point of interest is that large amounts of commercial compiled code were analyzed for clues as to which instructions would be the best candidates for performance optimization.

Against the Pentium, the 68060 could perform better on mixed code, Pentium's decoder could not issue an FP instruction every opportunity and hence the FPU was not superscalar as the ALUs were. If the 68060's non-pipelined FPU could accept an instruction, it could be issued one by the decoder. This meant that optimizing for the 68060 was easier, no rules prevented FP instructions from being issued whenever was convenient for the programmer other than well understood instruction latencies. However, with properly optimized and scheduled code, the Pentium's FPU was capable of double the clock for clock throughput of the 68060's FPU.

The 68060 was the last development of the 680x0 series for general purpose use, abandoned in favor of the PowerPC chips. It saw use in some late-model Amiga machines and Amiga accelerator cards as well as some Atari ST clones and a Falcon accelerator board (CT060), and very late models of the Alpha Microsystems multiuser computers before their migration to x86, but Apple Inc. and the Unix world had moved onto various RISC platforms by the time the '060 was available. The 68060 was introduced at 50 MHz on Motorola's 0.6 µm manufacturing process. A few years later it was shrunk to 0.42 µm and clock speed raised to 66 MHz and 75 MHz.

Developments of the basic core continue, intended for embedded systems. Here they are combined with a number of peripheral interfaces to reduce the overall complexity and power requirements of a design. A number of chips, each with different sets of interfaces, are sold under the name ColdFire and DragonBall.

History

The even numbers (68000, 68020, 68040, 68060) were reserved for major revisions to the 680x0 core architecture. The odd numbers (68010, 68030, 68050, 68070) were reserved for upgrades to the architecture of the previous chip. No 68050 or 68070 was ever produced by Motorola.

For example, the Motorola 68010 (and the obscure 68012) was a 68000 with improvements to the loop instruction and the ability to suspend then continue an instruction in the event of a page fault, enabling the use of virtual memory with the appropriate MMU hardware. There were, however, no major overhauls of the core architecture. Similarly, the Motorola 68030 was a process improvement on the 68020 with the MMU and a small data cache (256 bytes) moved on-chip. The 68030 was available in speed ratings up to 50 MHz.

The jump from the 68000/68010 to the 68020/68030, however, represented a major overhaul, with too many individual changes to list here.

By the time the 68060 was in production, Motorola had abandoned development of the 680x0-type chips in favor of the PowerPC. The 68060 was the last 680x0-type processor from Motorola.

There was a so-called 68070 processor, produced by Signetics (Philips), and was a modestly improved 68000 series processor, with a simple, on-chip MMU and I²C bus support. It came out long before the 68060, and was used mostly as an embedded processor in some consumer electronics items.

Usage

Perhaps its most memorable use was in American broadcast television graphics. Chyron's iNFiNiT!, Max!, and Maxine! series of television character generators used the 68060 as the main processor. These character generators were a fixture on many American television networks' affiliate stations.

In desktops, the 68060 was used in some variants of the Amiga 4000T produced by Amiga Technologies, and available as a third party upgrade for other Amiga models. It was also used in the Amiga clone DraCo non-linear video system.

The Q60 extended the Sinclair QL design similarly from the slowest start to the ultimate pace of the 68K architecture's capabilities; these 68060-based motherboards—at 66 MHz for the full 68060 or a non-FPU 68LC060 option overclocked to 80 MHz—are more than 100 times faster than the Sinclair QL while running the same operating systems.

The 68060 was also used in Nortel Meridian 1 Option 51, 61 and 81 large office PBX systems, powering the CP3 and CP4 core processor boards. A pair of these boards each sporting a 68060 could be used to make the PBX fault tolerant. This was a logical application as previous Meridian 1 cores used other Motorola chips. Nortel has since changed the architecture to use Intel processors.

Also the Motorola Vanguard 6560 multiprotocol router used a 50 MHz 68EC060 processor.

Motorola MVME-17x and Force Computer SYS68K VMEbus systems also used a 68060 CPU.

Variants

Variant	MMU present	FPU present
68060	MMU	FPU
68LC060	MMU	-
68EC060	-	-

Technical data

Work frequency	50, 60, 66, 75 MHz
Voltage supply	Vcore 3.3 V I/O 5 V
Temperature	−40 °C .. 70 °C (85 °C with the current mask)
Production process	Static-CMOS 0.6 μm and later 0.42 μm
Chip carrier	PGA 206 (compatible with 68040), TBGA 304 31*31*1.7P1.27
Address bus	32 bit
Data bus	32 bit
Instruction set	CISC
Cache	8 kB DCache (4-way associative) 8 kB ICache (4-way associative) 96 byte FIFO Instruction Buffer 256 Entry Branch Cache 64 Entry ATC* MMU Buffer (4-way associative)
Register	8 for Address operations 8 for Data operations
Transistors	~2,500,000
Performance	~88 Mips @ 66 MHz ~110 Mips @ 75 MHz ~36 MFlops @ 66 MHz

ATC = Address Translation Cache

References

• This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.

External links

• A paper describing the 68060 architecture