File talk:CMOS NAND Layout.svg

Where are the gate connections? The green (polysilicon) should have something connected to it! 146.169.7.32 (talk) 10:45, 30 April 2008 (UTC)[reply]

This diagram doesn't look right to me. Could an expert check it and either add a better explanation, or correct it.82.21.25.116 (talk) 16:49, 25 May 2008 (UTC)[reply]

I think this diagram is wrong - it shows there being additional dopant under the two poly strips. That doesn't make any sense, because then the drain and source are just tied together on all the transistors. Also, it's really confusing to have the separate n-doped region that's tied to VDD in the n-well. It would be nice to indicate that the red region in the top half and the background are actually conductive. Evanbro (talk) 02:13, 9 April 2009 (UTC)[reply]